Butterfly Labs test Wafer pictures and new chip details

butterfly-labsAfter yesterdays news that the bumping process is taking longer that expected BFL_Josh from Butterfly Labs has a few photos of what is meant to be the test wafer now at the ASIC testing plant getting ready to be cut.

The plan is to sacrifice one of the wafers that were included in batch one pictured below that contains 1000 of the 6000 ASIC chips that were supposed to be in batch one.


While the pictures of the wafers are very generic and could be of anything, Josh does let slip a few more details of the actual design of the chips in the caption of the photos where he says;-

Delicious wafer pie!

This is the test wafer containing approximately 1000 BFL designed 65nm hand routed double round SHA256 chips. Each chip contains 16 engines and measures approximately 7.5mm x 7.5mm. BFL_Josh

Josh also posted another photo of the wafer that I must admit looks a bit like bathroom tiles.


Neil Fincham, the MineForeman has over 20 years experience in the computer industry and runs the MineForeman mining operation for the co-op members. He is also very dyslexic, so he appreciates anyone pointing out spelling errors.

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One comment on “Butterfly Labs test Wafer pictures and new chip details
  1. R says:

    Should we be able to see the sections of the 16 engines in the transparency pic? I know the ASICs aren’t going to be as complex as CPUs, but I think some partitioning should still be visible on the dies.


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